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Digital VLSI Chip Design with Cadence and Synopsys CAD Tools, 1st edition

Published by Pearson (February 25, 2009) © 2010

  • Neil H. E. Weste Macquarie University and The University of Adelaide
  • David Money Harris
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Digital VLSI Chip Design with Cadence and Synopsys CAD Tools leads students through the complete process of building a ready-to-fabricate CMOS integrated circuit using popular commercial design software. Detailed tutorials include step-by-step instructions and screen shots of tool windows and dialog boxes. This hands-on book is for use in conjunction with a primary textbook on digital VLSI.
  • The VLSI CAD flow described in this book uses tools from two vendors: Cadence Design Systems, Inc. and Synopsys Inc.
  • Modeled after the Digital VLSI course at the University of Utah, this book's "soup-to-nuts" approach walks students through the entire experience of designing a complete chip project to the point where it can be fabricated.
  • Data files, scripts, information about the tools, and color versions of all the figures in the book, are available on the book’s Web site at: http://www.pearsonhighered.com/brunvand.

    • 1 Introduction 1
    1.1 CAD Tool Flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
    1.1.1 Custom VLSI and Cell Design Flow . . . . . . . . . . . . . . . . 3
    1.1.2 Hierarchical Cell/Block ASIC Flow . . . . . . . . . . . . . . . . 3
    1.2 What This Book Is and Isn’t . . . . . . . . . . . . . . . . . . . . . . . . 4
    1.3 Bugs in the Tools? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
    1.4 Tool Setup and Execution Scripts . . . . . . . . . . . . . . . . . . . . . . 6
    1.5 Typographical Conventions . . . . . . . . . . . . . . . . . . . . . . . . . 7

     

    2 Cadence DFII and ICFB 9
    2.1 Cadence Design Framework . . . . . . . . . . . . . . . . . . . . . . . . 9
    2.2 Starting Cadence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
    2.3 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

     

    3 Composer Schematic Capture 17
    3.1 Starting Cadence and Making a New
    Working Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
    3.2 Creating a New Cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
    3.2.1 Creating the Schematic View of a Full Adder . . . . . . . . . . . 19
    3.2.2 Creating the Symbol View of a Full Adder . . . . . . . . . . . . . 26
    3.2.3 Creating a Two-Bit Adder Using the FullAdder Bit . . . . . . . . 28
    3.3 Schematics that Use Transistors . . . . . . . . . . . . . . . . . . . . . . 31
    3.4 Printing Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
    3.4.1 Modifying PostScript Plot Files . . . . . . . . . . . . . . . . . . 38
    3.5 Variable, Pin, and Cell Naming Restrictions . . . . . . . . . . . . . . . . 39
    3.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

     

    4 Verilog Simulation 41
    4.1 Verilog Simulation of Composer Schematics . . . . . . . . . . . . . . . . 44
    4.1.1 Verilog-XL: Simulating a Schematic . . . . . . . . . . . . . . . . 45
    4.1.2 NC Verilog: Simulating a Schematic . . . . . . . . . . . . . . . . 65
    4.2 Behavioral Verilog Code in Composer . . . . . . . . . . . . . . . . . . . 69
    4.2.1 Generating a Behavioral View . . . . . . . . . . . . . . . . . . . 72
    4.2.2 Simulating a Behavioral View . . . . . . . . . . . . . . . . . . . 75
    4.3 Stand-Alone Verilog Simulation . . . . . . . . . . . . . . . . . . . . . . 76
    4.3.1 Verilog-XL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
    4.3.2 NC Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
    4.3.3 VCS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
    4.4 Timing in Verilog Simulations . . . . . . . . . . . . . . . . . . . . . . . 90
    4.4.1 Behavioral Versus Transistor Switch Simulation . . . . . . . . . . 94
    4.4.2 Behavioral Gate Timing . . . . . . . . . . . . . . . . . . . . . . 96
    4.4.3 Standard Delay Format (SDF) Timing . . . . . . . . . . . . . . . 99
    4.4.4 Transistor Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 101
    4.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

     

    5 Virtuoso Layout Editor 109
    5.1 An Inverter Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
    5.1.1 Starting Cadence icfb . . . . . . . . . . . . . . . . . . . . . . . . 111
    5.1.2 Making an Inverter Schematic . . . . . . . . . . . . . . . . . . . 111
    5.1.3 Making an Inverter Symbol . . . . . . . . . . . . . . . . . . . . 112
    5.2 Layout for an Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
    5.2.1 Creating a New layout View . . . . . . . . . . . . . . . . . . . . 113
    5.2.2 Drawing an nmos Transistor . . . . . . . . . . . . . . . . . . . . 113
    5.2.3 Drawing a pmos Transistor . . . . . . . . . . . . . . . . . . . . . 118
    5.2.4 Assembling the Inverter from the Transistor Layouts . . . . . . . 122
    5.2.5 Using Hierarchy in Layout . . . . . . . . . . . . . . . . . . . . . 128
    5.2.6 Virtuoso Command Overview . . . . . . . . . . . . . . . . . . . 130
    5.3 Printing Layouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
    5.4 Design Rule Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
    5.4.1 DIVA Design Rule Checking . . . . . . . . . . . . . . . . . . . . 134
    5.5 Generating an Extracted View . . . . . . . . . . . . . . . . . . . . . . . 140
    5.6 Layout Versus Schematic Checking (LVS) . . . . . . . . . . . . . . . . . 141
    5.6.1 Generating an analog-extracted View . . . . . . . . . . . . . . . 152
    5.7 Overall Cell Design Flow (So Far...) . . . . . . . . . . . . . . . . . . . . 153
    5.8 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

     

    6 Standard Cell Design Template 155
    6.1 Standard Cell Geometry Specification . . . . . . . . . . . . . . . . . . . 156
    6.2 Standard Cell I/O Pin Placement . . . . . . . . . . . . . . . . . . . . . . 158
    6.3 Standard Cell Transistor Sizing . . . . . . . . . . . . . . . . . . . . . . . 161
    6.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

     

    7 Spectre Analog Simulator 167
    7.1 Simulating a Schematic (Transient Simulation) . . . . . . . . . . . . . . 169
    7.2 Simulation with the Spectre Analog Environment . . . . . . . . . . . . . 171
    7.3 Simulating with a Config View . . . . . . . . . . . . . . . . . . . . . . . 176
    7.4 Mixed Analog/Digital Simulation . . . . . . . . . . . . . . . . . . . . . 182
    7.4.1 Final Words about Mixed-Mode Simulation . . . . . . . . . . . . 194
    7.5 DC Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
    7.5.1 Parametric Simulation . . . . . . . . . . . . . . . . . . . . . . . 204
    7.6 Power Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
    7.7 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

     

    8 Cell Characterization 215
    8.1 Liberty File Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
    8.1.1 Combinational Cell Definition . . . . . . . . . . . . . . . . . . . 219
    8.1.2 Sequential Cell Definition . . . . . . . . . . . . . . . . . . . . . 221
    8.1.3 Tristate Cell Definition . . . . . . . . . . . . . . . . . . . . . . . 228
    8.2 Cell Characterization with ELC . . . . . . . . . . . . . . . . . . . . . . 230
    8.2.1 Generating the ELC Netlist . . . . . . . . . . . . . . . . . . . . . 230
    8.2.2 Cell Naming and Encounter Library Characterizer . . . . . . . . 243
    8.2.3 Best, Typical, and Worst Case Characterization . . . . . . . . . . 244
    8.3 Cell Characterization with Spectre . . . . . . . . . . . . . . . . . . . . . 244
    8.4 Converting Liberty to Synopsys Database (db) Format . . . . . . . . . . 250
    8.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252

     

    9 Verilog Synthesis 253
    9.1 Synopsys Design Compiler Synthesis with dc shell . . . . . . 253
    9.1.1 Basic Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
    9.1.2 Scripted Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . 258
    9.1.3 Synopsys Design Vision GUI . . . . . . . . . . . . . . . . . . . . 267
    9.1.4 DesignWare Building Blocks . . . . . . . . . . . . . . . . . . . . 276
    9.2 Cadence RTL Compiler Synthesis . . . . . . . . . . . . . . . . . . . . . 277
    9.2.1 Scripted Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . 277
    9.2.2 Cadence RTL Compiler GUI . . . . . . . . . . . . . . . . . . . . 280
    9.3 Importing Structural Verilog into Cadence DFII . . . . . . . . . . . . . . 285
    9.4 Post-Synthesis Verilog Simulation . . . . . . . . . . . . . . . . . . . . . 288
    9.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295

     

    10 Abstract Generation 299
    10.1 Reading Your Library into Abstract . . . . . . . . . . . . . . . . . . . . 300
    10.2 Finding Pins in Your Cells . . . . . . . . . . . . . . . . . . . . . . . . . 303
    10.3 The Extract Step . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
    10.4 The Abstract Step . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
    10.5 LEF File Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
    10.6 Modifying the LEF File . . . . . . . . . . . . . . . . . . . . . . . . . . 309
    10.7 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311

     

    11 SOC Encounter Place and Route 313
    11.1 Encounter GUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
    11.1.1 Reading In the Design . . . . . . . . . . . . . . . . . . . . . . . 318
    11.1.2 Floorplanning . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
    11.1.3 Power Planning . . . . . . . . . . . . . . . . . . . . . . . . . . . 327
    11.1.4 Placing the Standard Cells . . . . . . . . . . . . . . . . . . . . . 333
    11.1.5 First Optimization Phase . . . . . . . . . . . . . . . . . . . . . . 333
    11.1.6 Clock Tree Synthesis . . . . . . . . . . . . . . . . . . . . . . . . 336
    11.1.7 Post-CTS Optimization . . . . . . . . . . . . . . . . . . . . . . . 338
    11.1.8 Final Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338
    11.1.9 Post-Route Optimization . . . . . . . . . . . . . . . . . . . . . . 343
    11.1.10 Adding Filler Cells . . . . . . . . . . . . . . . . . . . . . . . . . 345
    11.1.11 Checking the Result . . . . . . . . . . . . . . . . . . . . . . . . 345
    11.1.12 Saving and Exporting the Placed and Routed Cell . . . . . . . . . 349
    11.1.13 Reading the Cell Back into Virtuoso . . . . . . . . . . . . . . . . 352
    11.2 Design Import with Configuration Files . . . . . . . . . . . . . . . . . . 358
    11.2.1 Floorplanning . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361
    11.3 SOC Encounter Scripting . . . . . . . . . . . . . . . . . . . . . . . . . . 361
    11.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364

     

    12 Chip Assembly 367
    12.1 Module Routing with ccar . . . . . . . . . . . . . . . . . . . . . . . . . 367
    12.1.1 Preparing a Placement with Virtuoso-XL . . . . . . . . . . . . . . 369
    12.1.2 Invoking the ccar Router . . . . . . . . . . . . . . . . . . . . . . 374
    12.2 Core to Pad Frame Routing with ccar . . . . . . . . . . . . . . . . . . . 382
    12.2.1 Copy the Pad Frame . . . . . . . . . . . . . . . . . . . . . . . . 383
    12.2.2 Modify the Frame schematic View . . . . . . . . . . . . . . . . 385
    12.2.3 Modify the Frame layout View . . . . . . . . . . . . . . . . . . 390
    12.2.4 Routing the Core to Frame with ccar . . . . . . . . . . . . . . . 391
    12.2.5 Metal Density Issues . . . . . . . . . . . . . . . . . . . . . . . . 399
    12.3 Final GDSII Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . 399
    12.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405

     

    13 Design Example 409
    13.1 Tiny MIPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410
    13.2 Tiny MIPS: Flat Tool Flow . . . . . . . . . . . . . . . . . . . . . . . . . 416
    13.2.1 Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416
    13.2.2 Place and Route . . . . . . . . . . . . . . . . . . . . . . . . . . . 420
    13.2.3 Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432
    13.2.4 Final Assembly . . . . . . . . . . . . . . . . . . . . . . . . . . . 443
    13.3 Tiny MIPS: Hierarchical Tool Flow . . . . . . . . . . . . . . . . . . . . 446
    13.3.1 Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449
    13.3.2 Place and Route into a Macro Block . . . . . . . . . . . . . . . . 449
    13.3.3 Preparing Custom Circuits for Hierarchy . . . . . . . . . . . . . 451
    13.3.4 Generating Abstract Views for Blocks . . . . . . . . . . . . . . . 454
    13.3.5 Place and Route with Macro Blocks . . . . . . . . . . . . . . . . 456
    13.3.6 Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470
    13.3.7 Final Assembly . . . . . . . . . . . . . . . . . . . . . . . . . . . 470
    13.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470

     

    A Tool and Setup Scripts 475
    A.1 Cadence Tool Installation . . . . . . . . . . . . . . . . . . . . . . . . . . 476
    A.2 Cadence Setup Scripts . . . . . . . . . . . . . . . . . . . . . . . . . . . 478
    A.2.1 setup-cadence: Basic Cadence Setup . . . . . . . . . . . . . . . 478
    A.2.2 setup-ncsu: Cadence Setup with NCSU Extensions . . . . . . . . 481
    A.3 Shell Scripts for Cadence Tools . . . . . . . . . . . . . . . . . . . . . . . 482
    A.3.1 syn-abstract: Start the Abstract Tool . . . . . . . . . . . . . . . 482
    A.3.2 cad-alf2lib: Convert the alf Notation from Encounter Library Characterizer to lib Notation . . . . . . . . . 482
    A.3.3 cad-elc: Start the Encounter Library Characterizer . . . . . . . . 483
    A.3.4 cad-ncsu: Start the DFII (icfb) Environment . . . . . . . . . . . 484
    A.3.5 cad-soc: Start the SOC Encounter Place and Route Tool . . . . . 484
    A.3.6 sim-ncg: Startup Script for the NC Verilog Simulator, with GUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485
    A.3.7 sim-xlg: Startup Script for the Verilog-XL simulator, with GUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485
    A.3.8 sptr2elc: Perl Script for Converting Spectre Netlists to Encounter Library Characterizer Netlists . .  . 486
    A.3.9 syn-rtlg: Start the RTL Compiler Synthesis Tool, with GUI . . . 487
    A.4 Synopsys Tool Installation . . . . . . . . . . . . . . . . . . . . . . . . . 488
    A.5 Synopsys Setup Scripts . . . . . . . . . . . . . . . . . . . . . . . . . . . 489
    A.5.1 setup-synopsys: Basic Synopsys Setup . . . . . . . . . . . . . . 489
    A.6 Shell Scripts for Synopsys Tools . . . . . . . . . . . . . . . . . . . . . . 492
    A.6.1 sim-vcs: Startup Script for the VCS Verilog Simulator . . . . . . 492
    A.6.2 sim-simv: Startup Script for the simv Simulator Resulting from VCS Execution  . . . . . . . . . . . . . . 493
    A.6.3 syn-dc: Startup Script for Design Compiler Synthesis . . . . . . 494
    A.6.4 syn-dv: Startup Script for Design Compiler using the Design Vision GUI . .. . . . . . . . . 494
    A.7 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495

     

    B Scripts to Drive the Tools 497
    B.1 Tcl Script Basics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497
    B.2 Cadence Tool Scripts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499
    B.2.1 Encounter Library Characterizer Cell Characterization . . . . . . 500
    B.2.2 Cell Characterization with Spectre . . . . . . . . . . . . . . . . . 504
    B.2.3 SOC Encounter Place and Route . . . . . . . . . . . . . . . . . . 509
    B.2.4 RTL Compiler Synthesis . . . . . . . . . . . . . . . . . . . . . . 516
    B.2.5 ccar Chip Assembly Tool . . . . . . . . . . . . . . . . . . . . . 517
    B.3 Synopsys Tool Scripts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 519
    B.3.1 Synopsys Design Compiler Script Files . . . . . . . . . . . . . . 519
    B.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524

     

    C Technology and Cell Libraries 525
    C.1 NCSU Cadence Design Kit CDK1.5 Installation . . . . . . . . . . . . . . 525
    C.1.1 .cdsinit: Local Modifications . . . . . . . . . . . . . . . . . . . 526
    C.1.2 .cdsenv: Local Modifications . . . . . . . . . . . . . . . . . . . 529
    C.1.3 UofU TechLib ami06: Local Modifications . . . . . . . . . . . 530
    C.2 Example Standard Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . 535
    C.2.1 Example Liberty File . . . . . . . . . . . . . . . . . . . . . . . 536
    C.2.2 LEF File Technology Header . . . . . . . . . . . . . . . . . . . . 551
    C.2.3 LEF File MACRO Examples . . . . . . . . . . . . . . . . . . . . 554
    C.3 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 563
    Bibliography 565
    Index 567 

    Professor Erik Brunvand is an associate professor in the School of Computing at the University of Utah. He has interests in computer architecture and VLSI systems in general, and self-timed and asynchronous systems in particular. One aspect of his research involves compiling concurrent communicating programs into asynchronous VLSI circuits. The current system allows programs written in a subset of occam, a concurrent message-passing programming language based on CSP, to be automatically compiled into a set of self-timed circuit modules suitable for manufacture as an integrated circuit. He is also interested in investigating the effects of asynchrony on computer systems architecture at a higher level. To explore these ideas he is building a series of prototype asynchronous computer systems out of FPGA and custom VLSI chips.

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