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VHDL for Engineers, 1st edition
Published by Pearson (November 21, 2011) © 2009
- Kenneth L. Short University of New York-Stony Brook
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Suitable for use in a one- or two-semester course for computer and electrical engineering majors.
VHDL for Engineers teaches readers how to design and simulate digital systems using the hardware description language, VHDL. These systems are designed for implementation using programmable logic devices (PLDs) such as complex programmable logic devices (CPLDs) and field programmable gate arrays (FPGAs). The book focuses on writing VHDL design descriptions and VHDL testbenches. The steps in VHDL/PLD design methodology are also a key focus. Short presents the complex VHDL language in a logical manner, introducing concepts in an order that allows the readers to begin producing synthesizable designs as soon as possible.
Preface
1 Digital Design Using VHDL and PLDs 1
1.1
VHDL/PLD Design Methodology 11.2
Requirements Analysis and Specification 51.3
VHDL Design Description 61.4
Verification Using Simulation 111.5
Testbenches 131.6
Functional (Behavioral) Simulation 161.7
Programmable Logic Devices (PLDs) 181.8
SPLDs and the 22V10 211.9
Logic Synthesis for the Target PLD 271.10
Place-and-Route and Timing Simulation 311.11
Programming and Verifying a Target PLD 371.12
VHDL/PLD Design Methodology Advantages 381.13
VHDL’s Development 391.14
VHDL for Synthesis versus VHDL for Simulation 391.15
This Book’s Primary Objective 40Â
2 Entities , Architectures , and Coding Styles 44
2.1 Design Units, Library Units, and Design Entities 44
2.2
Entity Declaration 452.3
VHDL Syntax Definitions 472.4
Port Modes 502.5
Architecture Body 532.6
Coding Styles 552.7
Synthesis Results versus Coding Style 662.8
Levels of Abstraction and Synthesis 692.9
Design Hierarchy and Structural Style 71Â
3 Signals and Data Types 82
3.1
Object Classes and Object Types 823.2
Signal Objects 843.3
Scalar Types 883.4
Type Std_Logic 933.5
Scalar Literals and Scalar Constants 993.6
Composite Types 1003.7
Arrays 1013.8
Types Unsigned and Signed 1073.9
Composite Literals and Composite Constants 1103.10
Integer Types 1123.11
Port Types for Synthesis 1163.12
Operators and Expressions 118Â
4 Dataf low Style Combinational Design 123
4.1
Logical Operators 1234.2
Signal Assignments in Dataflow Style Architectures 1274.3
Selected Signal Assignment 1304.4
Type Boolean and the Relational Operators 1324.5
Conditional Signal Assignment 1344.6
Priority Encoders 1394.7
Don’t Care Inputs and Outputs 1404.8
Decoders 1444.9
Table Lookup 1474.10
Three-state Buffers 1514.11
Avoiding Combinational Loops 155Â
5 Behavi oral Style Combinational Design 165
5.1 Behavioral Style Architecture 165
5.2
Process Statement 1695.3
Sequential Statements 1705.4
Case Statement 1715.5
If Statement 1765.6
Loop Statement 1815.7
Variables 1855.8
Parity Detector Example 1885.9
Synthesis of Processes Describing Combinational Systems 193Â
6 Event-Driven Simulation 201
6.1
Simulator Approaches 2016.2
Elaboration 2036.3
Signal Drivers 2086.4
Simulator Kernel Process 2106.5
Simulation Initialization 2126.6
Simulation Cycles 2156.7
Signals versus Variables 2236.8
Delta Delays 2306.9
Delta Delays and Combinational Feedback 2356.10
Multiple Drivers 2396.11
Signal Attributes 241Â
7 Testbenche s for Combinational Designs 251
7.1
Design Verification 2517.2
Functional Verification of Combinational Designs 2557.3
A Simple Testbench 2557.4
Physical Types 2587.5
Single Process Testbench 2607.6
Wait Statements 2637.7
Assertion and Report Statements 2657.8
Records and Table Lookup Testbenches 2687.9
Testbenches That Compute Stimulus and Expected Results 2727.10
Predefined Shift Operators 2747.11
Stimulus Order Based on UUT Functionality 2767.12
Comparing a UUT to a Behavioral Intent Model 2797.13
Code Coverage and Branch Coverage 2817.14
Post-Synthesis and Timing Verifications for CombinationalDesigns 284
7.15
Timing Models Using VITAL and SDF 288Â
8 Latches and Flip - flops 304
8.1
Sequential Systems and Their Memory Elements 3048.2
D Latch 3088.3
Detecting Clock Edges 3158.4
D Flip-flops 3178.5
Enabled (Gated) Flip-flop 3248.6
Other Flip-flop Types 3288.7
PLD Primitive Memory Elements 3318.8
Timing Requirements and Synchronous Input Data 332Â
9 MultibitLatches, Registers, Counters,
and Memory 337
9.1
Multibit Latches and Registers 3379.2
Shift Registers 3409.3
Shift Register Counters 3469.4
Counters 3489.5
Detecting Non-clock Signal Edges 3609.6
Microprocessor Compatible Pulse Width Modulated SignalGenerator 366
9.7
Memories 370Â
10 Finite State Machines 380
10.1
Finite State Machines 38010.2
FSM State Diagrams 38610.3
Three Process FSM VHDL Template 38810.4
State Diagram Development 39210.5
Decoder for an Optical Shaft Encoder 40310.6
State Encoding and State Assignment 40910.7
Supposedly Safe FSMs 41410.8
Inhibit Logic FSM Example 41810.9
Counters as Moore FSMs 422Â
11 ASM Charts and RTL Design 431
11.1
Algorithmic State Machine Charts 43111.2
Converting ASM Charts to VHDL 4311.3
System Architecture 44111.4
Successive Approximation Register Design Example 44511.5
Sequential Multiplier Design 457Â
12 Subprograms 469
12.1
Subprograms 46912.2
Functions 47312.3
Procedures 48012.4
Array Attributes and Unconstrained Arrays 48412.5
Overloading Subprograms and Operators 49112.6
Type Conversions 494Â
13 Packages 501
13.1
Packages and Package Bodies 50113.2
Standard and De Facto Standard Packages 50513.3
Package STD_LOGIC_1164 51013.4
Package NUMERIC_STD (IEEE Std 1076.3) 51613.5
Package STD_LOGIC_ARITH 52313.6
Packages for VHDL Text Output 524Â
14 Testbenches for Sequential Systems 526
14.1
Simple Sequential Testbenches 52614.2
Generating a System Clock 52714.3
Generating the System Reset 53114.4
Synchronizing Stimulus Generation and Monitoring 53214.5
Testbench for Successive Approximation Register 53814.6
Determining a Testbench Stimulus for a Sequential System 54214.7
Using Procedures for Stimulus Generation 54514.8
Output Verification in Stimulus Procedures 55014.9
Bus Functional Models 55214.10
Response Monitors 560Â
15 Modular Design and Hierarchy 566
15.1
Modular Design, Partitioning, and Hierarchy 56615.2
Design Units and Library Units 57115.3
Design Libraries 57315.4
Using Library Units 57415.5
Direct Design Entity Instantiation 57715.6
Components and Indirect Design Entity Instantiation 58015.7 Configuration Declarations 587
15.8
Component Connections 59415.9
Parameterized Design Entities 59815.10
Library of Parameterized Modules (LPM) 60215.11
Generate Statement 605Â
16 More Design Examples 615
16.1
Microprocessor Compatible QuadratureDecoder/Counter Design 615
16.2
Verification of Quadrature Decoder/Counter 62416.3
Parameterized Quadrature Decoder/Counter 62816.4
Electronic Safe Design 63016.5
Verification of Electronic Safe 64416.6
Encoder for RF Transmitter Design 649Â
Appendix VHDL Attributes 659
Bibliography 663
Index
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