Computer Organization and Architecture, 11th edition

Published by Pearson (June 21, 2018) © 2019

  • William Stallings

eTextbook on Pearson+

ISBN-13: 9780135205129 (2018 update)
per month
Pay monthly or
pay undefined one-time
Buy nowOpens in a new tab
Instant access

eTextbook features

  • Instant access to eTextbook
  • Search, highlight, and notes
  • Create flashcards
Products list
$79.99
Rent nowOpens in a new tab

Details

  • A print text you can rent
  • Fulfilled by eCampus.com
  • Option to keep after rental expires

Computer Organization and Architecture comprehensively covers processor and computer design fundamentals. The text is about the structure and function of computers. Its purpose is to present, as clearly and completely as possible, the nature and characteristics of modern-day computer systems. Written in a clear, concise, and engaging style, author William Stallings provides a thorough discussion of the fundamentals of computer organization and architecture and relates these to contemporary design issues.

Incorporating brand-new material and strengthened pedagogy, the 11th Edition keeps students up to date with recent innovations and improvements in the field of computer organization and architecture. Subjects such as I/O functions and structures, RISC and parallel processors are thoroughly explored alongside real-world examples that enhance the text and build student interest.

I. Introduction

  1. Basic Concepts and Computer Evolution
    • 1.1 Organization and Architecture
    • 1.2 Structure and Function
    • 1.3 The IAS Computer
    • 1.4 Gates, Memory Cells, Chips, and Multichip Modules
    • 1.5 The Evolution of the Intel x86 Architecture
    • 1.6 Embedded Systems
    • 1.7 ARM Architecture
    • 1.8 Key Terms, Review Questions, and Problems
  2. Performance Concepts
    • 2.1 Designing for Performance
    • 2.2 Multicore, MICs, and GPGPUs
    • 2.3 Two Laws that Provide Insight: Ahmdahl’s Law and Little’s Law
    • 2.4 Basic Measures of Computer Performance
    • 2.5 Calculating the Mean
    • 2.6 Benchmarks and SPEC
    • 2.7 Key Terms, Review Questions, and Problems

II. The Computer System

  1. A Top-Level View of Computer Function and Interconnection
    • 3.1 Computer Components
    • 3.2 Computer Function
    • 3.3 Interconnection Structures
    • 3.4 Bus Interconnection
    • 3.5 Point-to-Point Interconnect
    • 3.6 PCI Express
    • 3.7 Key Terms, Review Questions, and Problems
  2. The Memory Hierarchy: Locality and Performance
    • 4.1 Principle of Locality
    • 4.2 Characteristics of Memory Systems
    • 4.3 The Memory Hierarchy
    • 4.4 Performance Modeling of a Multilevel Memory Hierarchy
    • 4.5 Key Terms, Review Questions, and Problems
  3. Cache Memory
    • 5.1 Cache Memory Principles
    • 5.2 Elements of Cache Design
    • 5.3 Intel x86 Cache Organization
    • 5.4 The IBM z13 Cache Organization
    • 5.5 Cache Performance Models
    • 5.6 Key Terms, Review Questions, and Problems
  4. Internal Memory
    • 6.1 Semiconductor Main Memory
    • 6.2 Error Correction
    • 6.3 DDR DRAM
    • 6.4 eDRAM
    • 6.5 Flash Memory
    • 6.6 Newer Nonvolatile Solid-State Memory Technologies
    • 6.7 Key Terms, Review Questions, and Problems
  5. External Memory
    • 7.1 Magnetic Disk
    • 7.2 RAID 221
    • 7.3 Solid State Drives
    • 7.4 Optical Memory
    • 7.5 Magnetic Tape
    • 7.6 Key Terms, Review Questions, and Problems
  6. Input/Output
    • 8.1 External Devices
    • 8.2 I/O Modules
    • 8.3 Programmed I/O
    • 8.4 Interrupt-Driven I/O
    • 8.5 Direct Memory Access
    • 8.6 Direct Cache Access
    • 8.7 I/O Channels and Processors
    • 8.8 External Interconnection Standards
    • 8.9 IBM z13 I/O Structure
    • 8.10 Key Terms, Review Questions, and Problems
  7. Operating System Support
    • 9.1 Operating System Overview
    • 9.2 Scheduling
    • 9.3 Memory Management
    • 9.4 Intel x86 Memory Management
    • 9.5 ARM Memory Management
    • 9.6 Key Terms, Review Questions, and Problems

III. Arithmetic and Logic

  1. Number Systems
    • 10.1 The Decimal System
    • 10.2 Positional Number Systems
    • 10.3 The Binary System
    • 10.4 Converting Between Binary and Decimal
    • 10.5 Hexadecimal Notation
    • 10.6 Key Terms and Problems
  2. Computer Arithmetic
    • 11.1 The Arithmetic and Logic Unit
    • 11.2 Integer Representation
    • 11.3 Integer Arithmetic
    • 11.4 Floating-Point Representation
    • 11.5 Floating-Point Arithmetic
  3. Digital Logic
    • 12.1 Boolean Algebra
    • 12.2 Gates
    • 12.3 Combinational Circuits
    • 12.4 Sequential Circuits
    • 12.5 Programmable Logic Devices
    • 12.6 Key Terms and Problems

IV. Instruction Sets and Assembly Language

  1. Instruction Sets: Characteristics and Functions
    • 13.1 Machine Instruction Characteristics
    • 13.2 Types of Operands
    • 13.3 Intel x86 and ARM Data Types
    • 13.4 Types of Operations
    • 13.5 Intel x86 and ARM Operation Types
    • 13.6 Key Terms, Review Questions, and Problems
    • Appendix 13: A Little-, Big-, and Bi-Endian
  2. Instruction Sets: Addressing Modes and Formats
    • 14.1 Addressing Modes
    • 14.2 x86 and ARM Addressing Modes
    • 14.3 Instruction Formats
    • 14.4 x86 and ARM Instruction Formats
    • 14.5 Key Terms, Review Questions, and Problems
  3. Assembly Language and Related Topics
    • 15.1 Assembly Language Concepts
    • 15.2 Motivation for Assembly Language Programming
    • 15.3 Assembly Language Elements
    • 15.4 Examples
    • 15.5 Types of Assemblers
    • 15.6 Assemblers
    • 15.7 Loading and Linking
    • 15.8 Key Terms, Review Questions, and Problems

V. The Central Processing Unit

  1. Processor Structure and Function
    • 16.1 Processor Organization
    • 16.2 Register Organization
    • 16.3 Instruction Cycle
    • 16.4 Instruction Pipelining
    • 16.5 Processor Organization for Pipelining
    • 16.6 The x86 Processor Family
    • 16.7 The ARM Processor
    • 16.8 Key Terms, Review Questions, and Problems
  2. Reduced Instruction Set Computers
    • 17.1 Instruction Execution Characteristics
    • 17.2 The Use of a Large Register File
    • 17.3 Compiler-Based Register Optimization
    • 17.4 Reduced Instruction Set Architecture
    • 17.5 RISC Pipelining
    • 17.6 MIPS R4000
    • 17.7 SPARC
    • 17.8 Processor Organization for Pipelining
    • 17.9 CISC, RISC, and Contemporary Systems
    • 17.10 Key Terms, Review Questions, and Problems
  3. Instruction-Level Parallelism and Superscalar Processors
    • 18.1 Overview
    • 18.2 Design Issues
    • 18.3 Intel Core Microarchitecture
    • 18.4 ARM Cortex-A8
    • 18.5 ARM Cortex-M3
    • 18.6 Key Terms, Review Questions, and Problems
  4. Control Unit Operation and Microprogrammed Control
    • 19.1 Micro-operations
    • 19.2 Control of the Processor
    • 19.3 Hardwired Implementation
    • 19.4 Microprogrammed Control
    • 19.5 Key Terms, Review Questions, and Problems

VI. Parallel Organization

  1. Parallel Processing
    • 20.1 Multiple Processors Organization
    • 20.2 Symmetric Multiprocessors
    • 20.3 Cache Coherence and the MESI Protocol
    • 20.4 Multithreading and Chip Multiprocessors
    • 20.5 Clusters
    • 20.6 Nonuniform Memory Access
    • 20.7 Key Terms, Review Questions, and Problems
  2. Multicore Computers
    • 21.1 Hardware Performance Issues
    • 21.2 Software Performance Issues
    • 21.3 Multicore Organization
    • 21.4 Heterogeneous Multicore Organization
    • 21.5 Intel Core i7-5960X
    • 21.6 ARM Cortex-A15 MPCore
    • 21.7 IBM z13 Mainframe
    • 21.8 Key Terms, Review Questions, and Problems

Appendix A: System Buses

  • A.1 Bus Structure
  • A.2 Multiple-Bus Hierarchies
  • A.3 Elements of Bus Design

Appendix B: Victim Cache Strategies

  • B.1 Victim Cache
  • B.2 Selective Victim Cache

Appendix C: Interleaved Memory

Appendix D: The International Reference Alphabet

Appendix E: Stacks

  • E.1 Stacks
  • E.2 Stack Implementation
  • E.3 Expression Evaluation

Appendix F: Recursive Procedures

  • F.1 Recursion
  • F.2 Activation Tree Representation
  • F.3 Stack Implementation
  • F.4 Recursion and Iteration

Appendix G: Additional Instruction Pipeline Topics

  • G.1 Pipeline Reservation Tables
  • G.2 Reorder Buffers
  • G.3 Tomasulo’s Algorithm
  • G.4 Scoreboarding
Glossary
References
Index

This publication contains markup to enable structural navigation and compatibility with assistive technologies. Images in the publication MAY NOT be fully described, which is a barrier to those who rely on alternative text descriptions. The publication supports text reflow and contains no content hazards known to cause adverse physical reactions.

Need help? Get in touch