The Art of Analog Layout, 3rd edition

For electrical engineering courses in analog layout.

A user-friendly presentation of analog layout 

The Art of Analog Layout covers the issues involved in successfully laying out analog integrated circuits. It  presents the material in an easy-to-understand way, without compromising detail or overwhelming the reader. Emphasis is placed on the cross-sections of devices and carrier-based models of device operation as compared to the geometric and schematic representation of devices.

The 3rd Edition is entirely rewritten to reflect changes in the field, including a new chapter on layout and new content on failure mechanisms, resistors, capacitors and inductors, the MOS transistor and more.

Hallmark features of this title

• A user-friendly presentation simplifies material without compromising detail or overwhelming the reader. Verbal explanations are favored over mathematical formulas, graphs are kept to a minimum, and line drawings are used.
• Consideration of failure mechanisms as crucial to layout. In addition to a dedicated chapter, further information on failure mechanisms is integrated into many chapters covering various devices.
• Fundamental representative processes include standard bipolar, polygate CMOS, and analog BiCMOS. The simplicity of bipolar and polygate CMOS should help readers understand the basics and apply their learning to more complicated processes. Analog BiCMOS, including DMOS transistors, is presented in detail (Ch. 4).

New and updated features of this title

• NEW: Chapter on layout covers the principles of layout editors; major interchange file formats; mask alignment and scalable design rules; and pattern generation (Ch. 3).
• NEW: Processing topics include silicon etching isolation systems; wafer bonding; chemical-mechanical polishing; and single- and dual-damascene copper (Ch. 2).
• NEW: Failure mechanisms content discusses self-heating and electrical filamentation; Blech, giant isotope, and latent antenna effects; electromigration of vias; the E, 1/E, and human-metal models; OVST; RoHS; PBTI; and substrate resistance (Ch. 5).
• NEW: Capacitors and inductors topics include fringing and junction capacitance; amorphous dielectrics; antireflective coatings; flux and trench capacitors; symmetrical layouts; and inductor parasitics (Ch. 7).
• NEW: Matching of resistors and capacitors includes proximity effects; microloading; iso-dense etch bias; the rule of dispersion; segmentation sensitivity; mechanical stress; piezoresistivity coefficients; thermal hysteresis; and long-term drift (Ch. 8).
• NEW: Applications of MOS transistors include conduction and switching losses; the rule of one-third; triangular approximation; gate propagation delays; SOA; the Spirito effect; embedded partial-finger senseFET; and DMOS, dielectric RESURF, and V-groove transistors (Ch. 13).